Design Verification (DV) Engineer
At Hudson River Trading (HRT) we are mathematicians, computer scientists, statisticians, physicists and engineers. We research and develop automated trading algorithms using advanced mathematical techniques. We have built one of the world's most sophisticated computing environments, and our researchers are at the forefront of innovation in the world of algorithmic trading.
Job Description
The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.
These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.
FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.
Responsibilities
- Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
- Writing detailed verification plans
- Quickly root-cause RTL bugs
- Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
- Managing test suites and continuous integration infrastructure
- Developing and improving open-source and internal tools
Qualifications
- Superb debug and analytical skills
- Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
- Experience with code and functional coverage collection/analysis
- Experience with SystemVerilog and industry-standard frameworks such as UVM
- Experience with Python
- Comfortable in a Linux environment
- Familiarity with Verilator and/or Cocotb preferred
- C++ experience is a plus
- A bachelor’s degree in computer science, electrical engineering, or a related field
Annual base salary range of $175,000 to $225,000. Pay (base and bonus) may vary depending on job-related skills and experience. A sign-on and discretionary performance bonus may be provided as part of the total compensation package, in addition to company-paid medical and/or other benefits.
The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.
These high performance designs require even higher performance verification. We are looking for experienced Design Verification (DV) engineers who are skilled at writing testbenches and building verification environments to exercise complex HDL. Our ideal candidate is not only an ace tester, but a practicing toolsmith. You know the EDA landscape and want to be part of a team actively working to rethink, redesign, and surpass the status quo. For example, members of our team are active maintainers of popular open source projects such as Slang, Verilator, and Cocotb.
FPGA and ASIC verification is part of an innovative, growing team at HRT which is integral to the success of our trading. You can expect to always be challenged by the ever-changing financial markets as you work to ensure correctness and robustness of our critical hardware in an extremely fast-paced, real-time environment. No financial experience is necessary.
Responsibilities
- Creating testbenches and tests for our hardware platform, leveraging a hybrid open-source/proprietary, highly flexible environment
- Writing detailed verification plans
- Quickly root-cause RTL bugs
- Collaborating directly with designers for rapid bringup of new projects and debugging of existing designs
- Managing test suites and continuous integration infrastructure
- Developing and improving open-source and internal tools
Qualifications
- Superb debug and analytical skills
- Professional experience (2+ years) in RTL functional verification for FPGA or ASIC
- Experience with code and functional coverage collection/analysis
- Experience with SystemVerilog and industry-standard frameworks such as UVM
- Experience with Python
- Comfortable in a Linux environment
- Familiarity with Verilator and/or Cocotb preferred
- C++ experience is a plus
- A bachelor’s degree in computer science, electrical engineering, or a related field
Annual base salary range of $175,000 to $225,000. Pay (base and bonus) may vary depending on job-related skills and experience. A sign-on and discretionary performance bonus may be provided as part of the total compensation package, in addition to company-paid medical and/or other benefits.
