Hardware Design Engineer
At Hudson River Trading (HRT) we are mathematicians, computer scientists, statisticians, physicists and engineers. We research and develop automated trading algorithms using advanced mathematical techniques. We have built one of the world's most sophisticated computing environments, and our researchers are at the forefront of innovation in the world of algorithmic trading.
Job Description
The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.
FPGAs and ASICs are critical pieces of our technology stack. We are looking for talented hardware developers to architect and design complex systems on a highly collaborative global team. In this role, you'll identify efficient ways to perform on-the-fly transformations of market data and implement models with complex data structures in RTL. Deep knowledge of SystemVerilog, FPGA internals and/or ASIC primitives, computer architecture, and vendor tool suites are essential to succeeding in this role. Expertise in networking protocols, CPU design, and/or machine learning accelerators is a big plus. No financial experience is necessary.
Responsibilities
- Collaborate with a cross-functional team to develop and deploy custom FPGA and/or ASIC solutions for a wide range of trading applications
- Investigate new technologies and tools
- Contribute to a nimble hardware development tech stack
Qualifications
- Ability to describe hardware designs at a high level, low level, or anywhere in between
- Brilliant design, optimization, debugging and problem solving skills
- Professional experience (2+ years) in RTL design for FPGA or ASIC
- Expert SystemVerilog development skills with a thorough understanding of the language
- Expert on low level FPGA or ASIC architectures, with a deep understanding of what makes them "tick"
- Skilled in network communications, processing pipelines, and/or machine learning
- Working knowledge of Python and/or C++
- Comfortable in a Linux environment
- Strong verification experience
- Familiarity with AMD Vivado is a plus
- A bachelor’s degree in computer science, electrical engineering, or a related field
Annual base salary range of $200,000 to $250,000. Pay (base and bonus) may vary depending on job-related skills and experience. A sign-on and discretionary performance bonus may be provided as part of the total compensation package, in addition to company-paid medical and/or other benefits.
The Hardware team at Hudson River Trading (HRT) creates high performance compute engines using FPGA and ASIC technology to drive low latency trading decisions on global markets. We build custom solutions across the spectrum of speed and smarts: from bespoke circuits to world-class machine learning accelerators.
FPGAs and ASICs are critical pieces of our technology stack. We are looking for talented hardware developers to architect and design complex systems on a highly collaborative global team. In this role, you'll identify efficient ways to perform on-the-fly transformations of market data and implement models with complex data structures in RTL. Deep knowledge of SystemVerilog, FPGA internals and/or ASIC primitives, computer architecture, and vendor tool suites are essential to succeeding in this role. Expertise in networking protocols, CPU design, and/or machine learning accelerators is a big plus. No financial experience is necessary.
Responsibilities
- Collaborate with a cross-functional team to develop and deploy custom FPGA and/or ASIC solutions for a wide range of trading applications
- Investigate new technologies and tools
- Contribute to a nimble hardware development tech stack
Qualifications
- Ability to describe hardware designs at a high level, low level, or anywhere in between
- Brilliant design, optimization, debugging and problem solving skills
- Professional experience (2+ years) in RTL design for FPGA or ASIC
- Expert SystemVerilog development skills with a thorough understanding of the language
- Expert on low level FPGA or ASIC architectures, with a deep understanding of what makes them "tick"
- Skilled in network communications, processing pipelines, and/or machine learning
- Working knowledge of Python and/or C++
- Comfortable in a Linux environment
- Strong verification experience
- Familiarity with AMD Vivado is a plus
- A bachelor’s degree in computer science, electrical engineering, or a related field
Annual base salary range of $200,000 to $250,000. Pay (base and bonus) may vary depending on job-related skills and experience. A sign-on and discretionary performance bonus may be provided as part of the total compensation package, in addition to company-paid medical and/or other benefits.
